The standard hardware description language VHDL has so far mostly been used for simulation and synthesis in this context, users rarely define arbitrary logic types of their own either because synthesis tools do not support them or because simulation is done at levels where all data have simple bit or bit vector types. In this patent application, it is shown how VHDL's logic definition capabilities can be exploited to define special logic types based on which several testability related design rules can be checked with a VHDL simulator.
Several approaches to design rule checking have been published (GoFB77, Bhav83, KnTr89, KHOM90, Varm90, Bidj91, Pelz92). A good classification can be found in (Pelz92). While differing in the methods, all of these approaches except (GoFB77) need some special purpose tool to perform the checks. The goal of this invention is to tap standard simulation resources for rule checking, thus avoiding the need for a special purpose tool. The idea to check simple design rules with a standard logic simulator was already presented in (GoFB77). This procedure was very limited, though, since it had to use the standard logic provided by the simulator. Based on VHDL's flexibility, our new method makes performing significantly more complex checks feasible.